The present invention relates to a variable-length coding device for compressing video data and, more particularly, to a variable-length coding device capable of coding video data at high speed.
It has been customary, in a variable-length coding device for video data compression to read out a predefined variable-length code which matches input video data, to sequentially shift the variable-length code, one bit at a time, depending on the number of bits of remaining valid data stored in the currently used address of a compressed data memory (i.e., where the final bit of the immediately preceding variable-length code was written), and to OR the resulting shifted variable-length code with the "remaining" data to produce combined compressed data suitable for storage, beginning with the currently used address. The problem with this procedure is that it consumes a substantial period of time when the variable-length code must be shifted a number of times. Particularly, when the variable-length code has two or three bytes, the processing time is doubled or tripled. Further, since data transfer to the compressed data memory occurs on a bit-by-bit basis, it is necessary to manage the address of the last data in the memory, again increasing the processing time.
In light of the above, Japanese Patent Laid-Open Publication No. 59-57576 discloses a procedure for promoting rapid variable-length coding. The procedure taught in this Laid-Open Publication uses a counter for counting the bits of the variable-length code to be stored and controls the shift on the basis of this count. Specifically, the variable-length code is shifted, two bits at a time, from the upper bits, and then is transferred to a memory. As for the last bit, whether the count of the counter is even or odd is determined. The last bit is shifted by two bits if the count is even or by one bit if it is odd and then transferred to the memory. Such a procedure successfully reduces the number of shifts. However, when the variable-length code has, for example, a great bit length, even this procedure needs a great number of shifts. This, coupled with the fact that whether or not the number of bits is even or odd must be determined, prevents the processing time from being sufficiently reduced.